\doxysection{stm32h7xx\+\_\+hal\+\_\+pwr.\+h}
\hypertarget{stm32h7xx__hal__pwr_8h_source}{}\label{stm32h7xx__hal__pwr_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_pwr.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_pwr.h}}
\mbox{\hyperlink{stm32h7xx__hal__pwr_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00064\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00095\ \textcolor{preprocessor}{\#define\ PWR\_PVD\_MODE\_NORMAL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000U)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00096\ \textcolor{preprocessor}{\#define\ PWR\_PVD\_MODE\_IT\_RISING\ \ \ \ \ \ \ \ \ \ \ \ (0x00010001U)\ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00099\ \textcolor{preprocessor}{\#define\ PWR\_PVD\_MODE\_EVENT\_RISING\ \ \ \ \ \ \ \ \ (0x00020001U)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00100\ \textcolor{preprocessor}{\#define\ PWR\_PVD\_MODE\_EVENT\_FALLING\ \ \ \ \ \ \ \ (0x00020002U)\ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00109\ \textcolor{preprocessor}{\#define\ PWR\_MAINREGULATOR\_ON\ \ \ \ \ \ (0U)}}
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\DoxyCodeLine{00127\ \textcolor{preprocessor}{\#define\ PWR\_STOPENTRY\_WFI\ \ (0x01U)}}
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\DoxyCodeLine{00283\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ tmpreg\ =\ READ\_BIT(PWR-\/>D3CR,\ PWR\_D3CR\_VOS);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00284\ \textcolor{preprocessor}{\ \ \ \ \ \ \}\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00285\ \textcolor{preprocessor}{\ \ \ \ \ \ UNUSED(tmpreg);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00286\ \textcolor{preprocessor}{\}\ while(0)}}
\DoxyCodeLine{00287\ \textcolor{preprocessor}{\#else\ }\textcolor{comment}{/*\ STM32H72xxx\ and\ STM32H73xxx\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00288\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VOLTAGESCALING\_CONFIG(\_\_REGULATOR\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00289\ \textcolor{preprocessor}{do\ \{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00290\ \textcolor{preprocessor}{\ \ \ \ \ \ \_\_IO\ uint32\_t\ tmpreg\ =\ 0x00;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00291\ \textcolor{preprocessor}{\ \ \ \ \ \ }\textcolor{comment}{/*\ Configure\ the\ Voltage\ Scaling\ */}\textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00292\ \textcolor{preprocessor}{\ \ \ \ \ \ MODIFY\_REG\ (PWR-\/>D3CR,\ PWR\_D3CR\_VOS,\ (\_\_REGULATOR\_\_));\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00293\ \textcolor{preprocessor}{\ \ \ \ \ \ }\textcolor{comment}{/*\ Delay\ after\ setting\ the\ voltage\ scaling\ */}\textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00294\ \textcolor{preprocessor}{\ \ \ \ \ \ tmpreg\ =\ READ\_BIT(PWR-\/>D3CR,\ PWR\_D3CR\_VOS);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00295\ \textcolor{preprocessor}{\ \ \ \ \ \ UNUSED(tmpreg);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00296\ \textcolor{preprocessor}{\}\ while(0)}}
\DoxyCodeLine{00297\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined(SYSCFG\_PWRCR\_ODEN)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00298\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (PWR\_SRDCR\_VOS)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00299\ }
\DoxyCodeLine{00377\ \textcolor{preprocessor}{\#if\ defined\ (DUAL\_CORE)\ }\textcolor{comment}{/*\ Dual\ core\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00378\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00379\ \textcolor{preprocessor}{(((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_PVDO)\ \ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ \ ==\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00380\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_AVDO)\ \ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ \ ==\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00381\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_ACTVOSRDY)\ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_ACTVOSRDY)\ \ ==\ PWR\_CSR1\_ACTVOSRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00382\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VOSRDY)\ \ \ \ \ ?\ ((PWR-\/>D3CR\ \&\ PWR\_D3CR\_VOSRDY)\ \ \ \ \ ==\ PWR\_D3CR\_VOSRDY)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00383\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SMPSEXTRDY)\ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_SMPSEXTRDY)\ \ \ ==\ PWR\_CR3\_SMPSEXTRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00384\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_BRR)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ \ \ ==\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00385\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_CPU\_HOLD)\ \ \ ?\ ((PWR-\/>CPU2CR\ \&\ PWR\_CPU2CR\_HOLD1F)\ ==\ PWR\_CPU2CR\_HOLD1F)\ \ :\(\backslash\)}}
\DoxyCodeLine{00386\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_CPU2\_HOLD)\ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_HOLD2F)\ \ \ ==\ PWR\_CPUCR\_HOLD2F)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00387\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB)\ \ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF)\ \ \ \ \ \ ==\ PWR\_CPUCR\_SBF)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00388\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG2\_SB)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPU2CR\ \&\ PWR\_CPU2CR\_SBF)\ \ \ \ ==\ PWR\_CPU2CR\_SBF)\ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00389\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_STOP)\ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_STOPF)\ \ \ \ ==\ PWR\_CPUCR\_STOPF)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00390\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG2\_STOP)\ \ \ \ \ \ ?\ ((PWR-\/>CPU2CR\ \&\ PWR\_CPU2CR\_STOPF)\ \ ==\ PWR\_CPU2CR\_STOPF)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00391\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB\_D1)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF\_D1)\ \ \ ==\ PWR\_CPUCR\_SBF\_D1)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00392\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG2\_SB\_D1)\ \ \ \ \ ?\ ((PWR-\/>CPU2CR\ \&\ PWR\_CPU2CR\_SBF\_D1)\ ==\ PWR\_CPU2CR\_SBF\_D1)\ \ :\(\backslash\)}}
\DoxyCodeLine{00393\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB\_D2)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF\_D2)\ \ \ ==\ PWR\_CPUCR\_SBF\_D2)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00394\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG2\_SB\_D2)\ \ \ \ \ ?\ ((PWR-\/>CPU2CR\ \&\ PWR\_CPU2CR\_SBF\_D2)\ ==\ PWR\_CPU2CR\_SBF\_D2)\ \ :\(\backslash\)}}
\DoxyCodeLine{00395\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_USB33RDY)\ \ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_USB33RDY)\ \ \ \ \ ==\ PWR\_CR3\_USB33RDY)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00396\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPH)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00397\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPL)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00398\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VBATH)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATH)\ \ \ \ \ \ \ \ ==\ PWR\_CR2\_VBATH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00399\ \textcolor{preprocessor}{\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATL)\ ==\ PWR\_CR2\_VBATL))}}
\DoxyCodeLine{00400\ \textcolor{preprocessor}{\#else\ }\textcolor{comment}{/*\ Single\ core\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00401\ \textcolor{preprocessor}{\#if\ defined\ (PWR\_CPUCR\_SBF\_D2)\ }\textcolor{comment}{/*\ STM32H72x,\ STM32H73x,\ STM32H74x\ and\ STM32H75x\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00402\ \textcolor{preprocessor}{\#if\ defined\ (SMPS)\ }\textcolor{comment}{/*\ STM32H725\ and\ STM32H735\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00403\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00404\ \textcolor{preprocessor}{(((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_PVDO)\ \ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00405\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_AVDO)\ \ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00406\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_ACTVOSRDY)\ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_ACTVOSRDY)\ ==\ PWR\_CSR1\_ACTVOSRDY)\ \ :\(\backslash\)}}
\DoxyCodeLine{00407\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VOSRDY)\ \ \ \ \ ?\ ((PWR-\/>D3CR\ \&\ PWR\_D3CR\_VOSRDY)\ \ \ \ ==\ PWR\_D3CR\_VOSRDY)\ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00408\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SMPSEXTRDY)\ ?\ ((PWR-\/>CR3\ \&\ PWR\_FLAG\_SMPSEXTRDY)\ ==\ PWR\_FLAG\_SMPSEXTRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00409\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_BRR)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ \ ==\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00410\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB)\ \ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF)\ \ \ \ \ ==\ PWR\_CPUCR\_SBF)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00411\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_STOP)\ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_STOPF)\ \ \ ==\ PWR\_CPUCR\_STOPF)\ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00412\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB\_D1)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF\_D1)\ \ ==\ PWR\_CPUCR\_SBF\_D1)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00413\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB\_D2)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF\_D2)\ \ ==\ PWR\_CPUCR\_SBF\_D2)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00414\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_USB33RDY)\ \ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_USB33RDY)\ \ \ \ ==\ PWR\_CR3\_USB33RDY)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00415\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPH)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00416\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPL)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00417\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VBATH)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_VBATH)\ \ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00418\ \textcolor{preprocessor}{\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATL)\ ==\ PWR\_CR2\_VBATL))}}
\DoxyCodeLine{00419\ \textcolor{preprocessor}{\#else\ }\textcolor{comment}{/*\ STM32H723,\ STM32H733,\ STM32H742,\ STM32H743,\ STM32H750\ and\ STM32H753\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00420\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00421\ \textcolor{preprocessor}{(((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_PVDO)\ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00422\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_AVDO)\ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00423\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_ACTVOSRDY)\ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_ACTVOSRDY)\ ==\ PWR\_CSR1\_ACTVOSRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00424\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VOSRDY)\ \ \ \ ?\ ((PWR-\/>D3CR\ \&\ PWR\_D3CR\_VOSRDY)\ \ \ \ ==\ PWR\_D3CR\_VOSRDY)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00425\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SCUEN)\ \ \ \ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_SCUEN)\ \ \ \ \ \ \ ==\ PWR\_CR3\_SCUEN)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00426\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_BRR)\ \ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ \ ==\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00427\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF)\ \ \ \ \ ==\ PWR\_CPUCR\_SBF)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00428\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_STOP)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_STOPF)\ \ \ ==\ PWR\_CPUCR\_STOPF)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00429\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB\_D1)\ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF\_D1)\ \ ==\ PWR\_CPUCR\_SBF\_D1)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00430\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB\_D2)\ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF\_D2)\ \ ==\ PWR\_CPUCR\_SBF\_D2)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00431\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_USB33RDY)\ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_USB33RDY)\ \ \ \ ==\ PWR\_CR3\_USB33RDY)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00432\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPH)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00433\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPL)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00434\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VBATH)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_VBATH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00435\ \textcolor{preprocessor}{\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATL)\ ==\ PWR\_CR2\_VBATL))}}
\DoxyCodeLine{00436\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (SMPS)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00437\ \textcolor{preprocessor}{\#else\ }\textcolor{comment}{/*\ STM32H7Axxx\ and\ STM32H7Bxxx\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00438\ \textcolor{preprocessor}{\#if\ defined\ (SMPS)\ }\textcolor{comment}{/*\ STM32H7AxxQ\ and\ STM32H7BxxQ\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00439\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00440\ \textcolor{preprocessor}{(((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_PVDO)\ \ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00441\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_AVDO)\ \ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00442\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_ACTVOSRDY)\ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_ACTVOSRDY)\ ==\ PWR\_CSR1\_ACTVOSRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00443\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_BRR)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ \ ==\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00444\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VOSRDY)\ \ \ \ \ ?\ ((PWR-\/>SRDCR\ \&\ PWR\_SRDCR\_VOSRDY)\ \ ==\ PWR\_SRDCR\_VOSRDY)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00445\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_STOP)\ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_STOPF)\ \ \ ==\ PWR\_CPUCR\_STOPF)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00446\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB)\ \ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF)\ \ \ \ \ ==\ PWR\_CPUCR\_SBF)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00447\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_MMCVDO)\ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_MMCVDO)\ \ \ \ ==\ PWR\_CSR1\_MMCVDO)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00448\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SMPSEXTRDY)\ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_SMPSEXTRDY)\ \ ==\ PWR\_CR3\_SMPSEXTRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00449\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_USB33RDY)\ \ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_USB33RDY)\ \ \ \ ==\ PWR\_CR3\_USB33RDY)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00450\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPH)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00451\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPL)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00452\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VBATH)\ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_VBATH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00453\ \textcolor{preprocessor}{\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATL)\ ==\ PWR\_CR2\_VBATL))}}
\DoxyCodeLine{00454\ \textcolor{preprocessor}{\#else\ }\textcolor{comment}{/*\ STM32H7Axx\ and\ STM32H7Bxx\ lines\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00455\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00456\ \textcolor{preprocessor}{(((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_PVDO)\ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_PVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00457\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_AVDO)\ \ \ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ ==\ PWR\_CSR1\_AVDO)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00458\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_ACTVOSRDY)\ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_ACTVOSRDY)\ ==\ PWR\_CSR1\_ACTVOSRDY)\ :\(\backslash\)}}
\DoxyCodeLine{00459\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_BRR)\ \ \ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ \ ==\ PWR\_CR2\_BRRDY)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00460\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VOSRDY)\ \ \ \ ?\ ((PWR-\/>SRDCR\ \&\ PWR\_SRDCR\_VOSRDY)\ \ ==\ PWR\_SRDCR\_VOSRDY)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00461\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SCUEN)\ \ \ \ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_SCUEN)\ \ \ \ \ \ \ ==\ PWR\_CR3\_SCUEN)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00462\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_STOP)\ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_STOPF)\ \ \ ==\ PWR\_CPUCR\_STOPF)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00463\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_SB)\ \ \ \ \ \ \ \ ?\ ((PWR-\/>CPUCR\ \&\ PWR\_CPUCR\_SBF)\ \ \ \ \ ==\ PWR\_CPUCR\_SBF)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00464\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_MMCVDO)\ \ \ \ ?\ ((PWR-\/>CSR1\ \&\ PWR\_CSR1\_MMCVDO)\ \ \ \ ==\ PWR\_CSR1\_MMCVDO)\ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00465\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_USB33RDY)\ \ ?\ ((PWR-\/>CR3\ \&\ PWR\_CR3\_USB33RDY)\ \ \ \ ==\ PWR\_CR3\_USB33RDY)\ \ \ :\(\backslash\)}}
\DoxyCodeLine{00466\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPH)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00467\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_TEMPL)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ \ ==\ PWR\_CR2\_TEMPL)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00468\ \textcolor{preprocessor}{\ ((\_\_FLAG\_\_)\ ==\ PWR\_FLAG\_VBATH)\ \ \ \ \ ?\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATH)\ \ \ \ \ \ \ ==\ PWR\_CR2\_VBATH)\ \ \ \ \ \ :\(\backslash\)}}
\DoxyCodeLine{00469\ \textcolor{preprocessor}{\ ((PWR-\/>CR2\ \&\ PWR\_CR2\_VBATL)\ ==\ PWR\_CR2\_VBATL))}}
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\DoxyCodeLine{00502\ \textcolor{preprocessor}{\ \ \ \ \ SET\_BIT(PWR-\/>CPUCR,\ PWR\_CPUCR\_CSSF);\ \ \ \(\backslash\)}}
\DoxyCodeLine{00503\ \textcolor{preprocessor}{\ \ \ \ \ SET\_BIT(PWR-\/>CPU2CR,\ PWR\_CPU2CR\_CSSF);\ \(\backslash\)}}
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\DoxyCodeLine{00671\ \textcolor{comment}{/*\ Include\ PWR\ HAL\ Extension\ module\ */}}
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\DoxyCodeLine{00674\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00682\ \textcolor{comment}{/*\ Initialization\ and\ de-\/initialization\ functions\ *****************************/}}
\DoxyCodeLine{00683\ \textcolor{keywordtype}{void}\ HAL\_PWR\_DeInit\ \ \ \ \ \ \ \ \ \ \ \ (\textcolor{keywordtype}{void});}
\DoxyCodeLine{00684\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnableBkUpAccess\ \ (\textcolor{keywordtype}{void});}
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\DoxyCodeLine{00693\ \textcolor{comment}{/*\ Peripheral\ Control\ functions\ \ **********************************************/}}
\DoxyCodeLine{00694\ \textcolor{comment}{/*\ PVD\ configuration\ */}}
\DoxyCodeLine{00695\ \textcolor{keywordtype}{void}\ HAL\_PWR\_ConfigPVD\ \ (\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_p_w_r___p_v_d_type_def}{PWR\_PVDTypeDef}}\ *sConfigPVD);}
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\DoxyCodeLine{00698\ }
\DoxyCodeLine{00699\ \textcolor{comment}{/*\ WakeUp\ pins\ configuration\ */}}
\DoxyCodeLine{00700\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnableWakeUpPin\ \ (uint32\_t\ WakeUpPinPolarity);}
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\DoxyCodeLine{00703\ \textcolor{comment}{/*\ Low\ Power\ modes\ entry\ */}}
\DoxyCodeLine{00704\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnterSTOPMode\ \ \ \ (uint32\_t\ Regulator,\ uint8\_t\ STOPEntry);}
\DoxyCodeLine{00705\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnterSLEEPMode\ \ \ (uint32\_t\ Regulator,\ uint8\_t\ SLEEPEntry);}
\DoxyCodeLine{00706\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnterSTANDBYMode\ (\textcolor{keywordtype}{void});}
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\DoxyCodeLine{00708\ \textcolor{comment}{/*\ Power\ PVD\ IRQ\ Handler\ */}}
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\DoxyCodeLine{00710\ \textcolor{keywordtype}{void}\ HAL\_PWR\_PVDCallback\ \ \ \ (\textcolor{keywordtype}{void});}
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\DoxyCodeLine{00712\ \textcolor{comment}{/*\ Cortex\ System\ Control\ functions\ \ *******************************************/}}
\DoxyCodeLine{00713\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnableSleepOnExit\ \ (\textcolor{keywordtype}{void});}
\DoxyCodeLine{00714\ \textcolor{keywordtype}{void}\ HAL\_PWR\_DisableSleepOnExit\ (\textcolor{keywordtype}{void});}
\DoxyCodeLine{00715\ \textcolor{keywordtype}{void}\ HAL\_PWR\_EnableSEVOnPend\ \ \ \ (\textcolor{keywordtype}{void});}
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\DoxyCodeLine{00744\ \textcolor{comment}{/*\ Private\ macros\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00752\ \textcolor{comment}{/*\ Check\ PVD\ level\ parameter\ */}}
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\DoxyCodeLine{00771\ \textcolor{comment}{/*\ Check\ low\ power\ regulator\ parameter\ */}}
\DoxyCodeLine{00772\ \textcolor{preprocessor}{\#define\ IS\_PWR\_REGULATOR(REGULATOR)\ (((REGULATOR)\ ==\ PWR\_MAINREGULATOR\_ON)\ \ \ ||\(\backslash\)}}
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\DoxyCodeLine{00775\ \textcolor{comment}{/*\ Check\ low\ power\ mode\ entry\ parameter\ */}}
\DoxyCodeLine{00776\ \textcolor{preprocessor}{\#define\ IS\_PWR\_SLEEP\_ENTRY(ENTRY)\ (((ENTRY)\ ==\ PWR\_SLEEPENTRY\_WFI)\ ||\(\backslash\)}}
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\DoxyCodeLine{00779\ \textcolor{comment}{/*\ Check\ low\ power\ mode\ entry\ parameter\ */}}
\DoxyCodeLine{00780\ \textcolor{preprocessor}{\#define\ IS\_PWR\_STOP\_ENTRY(ENTRY)\ (((ENTRY)\ ==\ PWR\_STOPENTRY\_WFI)\ ||\(\backslash\)}}
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